The data reveals a startling imbalance. ASML's order backlog has swelled beyond €40 billion, a figure that represents years of EUV lithography machine production. TSMC, the sole manufacturer of the world's most advanced AI chips, has responded by accelerating its capital expenditure to over $30 billion annually. Yet the market’s collective sentiment echoes a single refrain: not enough. This isn't market hysteria. It is a cold, structural truth rooted in the physics of semiconductor manufacturing, the geometry of supply chains, and the inherent lag between capital deployment and output.
### Context: The Architecture of AI’s Physical Layer To understand the gap, one must first grasp the machinery. ASML’s extreme ultraviolet (EUV) lithography systems are the only tools capable of etching the nanometer-scale transistors required for NVIDIA’s Blackwell, AMD’s MI300, and every other high-end AI accelerator. Each machine costs over $200 million, takes 18 months to build, and requires a supply chain spanning Carl Zeiss optics in Germany, Cymer light sources in the US, and precision mechanics in the Netherlands. TSMC, in turn, is the sole foundry capable of mass-producing these chips at scale. Their 3nm (N3) and 5nm (N5) fabs run at >95% utilization, leaving zero slack for unplanned demand.
The narrative of a “second wave” of AI—shifting from training-focused hyperscaler deployments to inference at the edge—only amplifies the tension. Training chips consume compute in bursts; inference chips need continuous, cost-efficient throughput. This transition multiplies the number of chips required per application, yet the supply infrastructure was built for a world where AI was a niche research tool. The result is a demand curve that far outpaces the linear output capacity of ASML’s fab and TSMC’s cleanrooms.
### Core: The On-Chain Evidence of Capacity Lag Deconstructing the imbalance requires stepping beyond press releases and into the hard data of manufacturing timelines. Let’s trace the critical path.
ASML’s annual EUV output has plateaued at roughly 50 to 60 units per year, with a target of 90+ by 2025-2026. But each new EUV machine must be qualified by TSMC before it can enter production—a process that takes 12 to 18 months. Even after qualification, TSMC requires another 6 to 9 months to ramp yield on a new node to commercially viable levels. That means any new EUV capacity ordered today will not contribute to AI chip supply until late 2026 at the earliest.
Now correlate this with demand. NVIDIA alone shipped over 1 million H100 GPUs in 2023 and is expected to double that with B200 in 2024. Each B200 GPU is a complex multi-die package requiring advanced CoWoS-L packaging, which itself is a bottleneck. TSMC’s CoWoS capacity in 2023 was around 120,000 units per quarter; by 2025 it may reach 300,000. But each B200 uses multiple CoWoS interposers, and the demand from cloud giants (Microsoft, AWS, Google) far exceeds even those expanded numbers. The data shows a compound annual growth rate in demand of over 80%, versus a capacity CAGR of roughly 30-35% for advanced nodes and packaging.
Furthermore, ASML’s High-NA EUV—the next-generation machine needed for 2nm and below—is not yet in volume production. Only a handful of experimental units have shipped. The learning curve for High-NA is steeper than for standard EUV, meaning the first several fabs using this equipment will likely see lower yields and slower ramp times. This introduces another layer of latency that no amount of capital can immediately compress.
Let’s talk about yield rates. TSMC’s N3 yields are estimated at 70-80%—good, but not symmetrical to N5’s >90%. That 10-20% yield gap means that for every 100 wafers started, 10-20 more dies must be discarded, reducing effective capacity below nominal. With AI chips often being the largest dies on a wafer, any yield shortfall directly reduces the number of functional chips. The market “still not enough” feeling is thus encoded in the mathematics of defect density.
Additionally, the supply chain for EUV resists elasticity. Carl Zeiss can only produce a limited number of optical mirrors per year. The coating processes for these mirrors require years of accumulated know-how. ASML can hire more engineers, but the constraint is not manpower—it is the physics of polishing materials to atomic precision. This is not a software issue; it is a hardware bottleneck that scales linearly, not exponentially.
### Contrarian: The Misreading of Correlation as Causation The prevailing assumption is that more capital spending will solve the shortage. But the data shows a historical pattern: semiconductor capacity expansion has a four-year lag from announcement to volume production. In 2021, TSMC announced a $100 billion capex plan over three years. Most of that fab space is only now coming online in 2024. The AI demand spike of 2023 was met by fabs planned in 2019. This delay creates a recurring boom-bust cycle: over-ordering during shortages leads to double-ordering, which inflates the perceived demand, which then causes overcapacity when the new fabs finally start producing. The market’s “not enough” today may actually be a distortion caused by hyperscalers ordering 3x their actual needs to secure allocation. When those orders normalize, the newly built capacity could become surplus.
Furthermore, the assumption that TSMC’s lead over Samsung and Intel will persist indefinitely is a fragile bet. Intel’s foundry push, though behind schedule, is building capacity with ASML’s High-NA tools as well. If Intel achieves parity at 18A, the duopoly could become a triopoly, shifting negotiation power and potentially slowing TSMC’s pricing growth. But more importantly, the current shortage is not solely about total wafer output—it is about packaging. CoWoS capacity is physically constrained by substrate suppliers like Unimicron and Ibiden. These companies face their own capital and talent limitations. Expanding CoWoS requires building entirely new substrate factories, which take 2-3 years and hundreds of millions in investment. TSMC cannot solve this alone; it depends on its own supply chain, which is equally constrained.
Geopolitical fragmentation adds another counter-intuitive twist. The CHIPS Act and export controls force TSMC and ASML to build factories in the US, Japan, and Germany. These greenfield projects are slower and more expensive than building in Taiwan. The Arizona fab has already faced delays and labor shortages. Diversification reduces single-point-of-failure risk but increases cost-per-wafer and extends the lead time for capacity expansion. In effect, the effort to de-risk the supply chain is actually making the shortage worse in the short to medium term.
### Takeaway: The Signal to Watch Is Not CAPEX—It’s Yield For an on-chain analyst, the ultimate metric is not the number of EUV machines shipped, but the yield rate on TSMC’s N2 and CoWoS-L lines. Yield is the real-time ledger of manufacturing health. If yields plateau below 70% for more than two consecutive quarters, the shortage will persist beyond 2027, regardless of capex. If yields improve faster than expected, the surplus risk rises. The market is currently pricing in a linear resolution—but the data suggests a nonlinear path, full of phase transitions.
The next signal: track ASML’s backlog aging and TSMC’s monthly revenue breakdown by node. If N3 revenue grows faster than N5 revenue, it signals that demand is shifting to older nodes for inference, which could ease the bottleneck. If N5 revenue accelerates instead, the squeeze continues. The chain never lies—only the narratives about it do. When the data says the bottleneck is hard physics, the only rational hedge is time.
Decoding the algorithmic chaos of semiconductor supply traps requires patience, not panic. The second wave of AI will arrive, but not on the market’s preferred timeline. Reconstructing the timeline of a capacity ramp exposes the gap between expectation and reality. The data has spoken. The rest is noise.